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AR# 22171

9.1i XST - Does XST support Verilog specify blocks?

描述

Specify blocks provide a way to annotate timing constraints inside of the Verilog code. Does XST support specify blocks?

解决方案

No, XST does not support specify blocks. The only methods available for passing timing constraints are through attribute passing and through the UCF.

There is no fix scheduled for this issue.

AR# 22171
日期 12/15/2012
状态 Active
Type 综合文章
的页面