We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22179

Virtex-4 FX - How do I determine PowerPC startup, hang, or reset issues?


Keywords: PPC, PPC405, 0x00000000, XMD, connect

How do I determine PowerPC (PPC) startup issues?


To determine PPC startup issues, use the following guidelines:

- On power up, PPC does not boot as follows:
* Independent of frequency or configuration mode
* Independent of JTAG chain setup (with or without JTAGPPC)
* With or without DCMs

- FPGA configures correctly, and FPGA logic works

- Asserting PPC reset has no effect

- XMD cannot connect to the PPC

- Instrumented design with ChipScope:
* Instruction side PPC Request to 0xFFFFFFFC is followed by request 0x????0800 (observe behavior with PLB IBA or ILA on C405DBGWBIAR port)

- Multiple reconfigurations might enable PPC startup

- After successful power on, subsequent reconfigurations (without power sequencing) do not exhibit PPC startup problem

In EDK version 6.xi and 7.1i, you need to add the following PPC Core parameter to the ppc405_virtex4_v1_00_a in the MHS file for your design:

PARAMETER C_APU_CONTROL = 0b1101111000000000

This parameter is added to the "ppc405_virtex4_v2_1_0.mpd" file in EDK 8.1i as the default. Also, ppc405_virtex4_v1_01_a should be used in EDK 8.1i.

NOTE: You do not need to set the C_APU_CONTROL parameter for Virtex-2 Pro designs.
AR# 22179
日期 08/31/2007
状态 Active
Type 综合文章