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AR# 22224

Virtex-II Pro MGT - Does the silicon support a single-ended BREFCLK?


General Description:

When I try to map a design with a single-ended BREFCLK, I receive the following error:

ERROR:LIT - BREFCLK2 of GT symbol "MY_MGT_INST" is chosen and must be driven by differential input buffer. The current driver of this pin is pin O of IBUF symbol "BREFCLK_IBUF" [output signal=brefclk).

Is this due to a software limitation or lack of silicon support?


The silicon will not support a single-ended BREFCLK. A differential input must be used for this signal.

AR# 22224
日期 12/15/2012
状态 Archive
Type 综合文章