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AR# 22226

ISE 7.1i - How does the new pin pre-assignment feature work?


Keyword: DRC, PhysDesignRules, 367, Warning, Pin, Preassignment, Pre assignment, Pre-assignment, Map, trim, BitGen

ISE 7.1i has new pin pre-assignment capabilities. How do these work, and how should they be used?


New functionality has been added in ISE 7.1i that allows you to assign pin locations before the design is complete. In previous versions, XST would remove unused ports causing NGDBuild errors. XST now leaves unused ports so that you can complete implementation with a partial design. MAP will not trim the unused ports if there is a corresponding LOC constraint.

This functionality was added with the assumption that all ports would be used before a BIT file was created. If BitGen is run with these ports still unused, errors similar to the following occur:

"WARNING:PhysDesignRules:367 - The signal <B5C1_D(40)_IBUF> is incomplete. The signal does not drive any load pins in the design."

If the signal name contains _IBUF or _OBUF, it is likely caused by this feature. To avoid this error, either remove the unused ports from your design or the corresponding LOC constraints prior to generating the programming file.

AR# 22226
日期 12/15/2012
状态 Active
Type 综合文章