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AR# 22318

Virtex-4/-5 - What is the minimum frequency for a PMCD clock input?

描述

What is the minimum frequency for clock inputs to a PMCD?

解决方案


There is no restriction on the minimum frequency of Virtex-4 FPGA PMCD clock inputs. This is documented in the Virtex-4 FPGA Data Sheet.
If you use the Virtex-5 FPGA PLL in PMCD legacy mode, there is a minimum input frequency specification of 1 MHz. This is mentioned in the Virtex-5 FPGA Data Sheet.
AR# 22318
日期 12/15/2012
状态 Active
Type 综合文章
的页面