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AR# 22402

8.1i XST - Inverters are missing in the RTL View

描述

Keywords: AND, inverter, RTL Viewer

When I synthesize a design with XST that contains the following lines:

clock <= (not reset) and (not csmodul);

the inverters are not displayed in the RTL Viewer; there is only 1 AND gate without any inverter.

解决方案

This problem has been fixed in the latest 8.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.1i Service Pack 1.
AR# 22402
日期 05/11/2007
状态 Archive
Type 综合文章
的页面