CPLD fitter may require more than 200 Megs of RAM while trying to fit a design in a larger device such as 95216 or 95288.
The underlying cause could be the user's UCF file, if it contains a lot of global timespecs which cause the fitter to trace a large number of paths, greater than 100,000 in some cases.
解决方案
1
Use more specific Timespecs in your file as recommended by Xilinx.