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AR# 22473

7.1i NetGen - Incorrect simulation model generated for ODDR Tristate control primitive

描述

Keywords: same, edge, timing, SimPrim

If I use an ODDR primitive to perform Tristate control in my design and set up the ODDR primitive to operate in "same edge" mode as described in the Virtex-4 User Guide:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=User+Guides/FPGA+Device+Families/Virtex-4

I see that the Post-PAR timing simulation is not working correctly. It seems an incorrect simulation model has been generated for this part of the design.

解决方案

This issue affects only the ODDR primitive when used for Tristate control and with the "same edge" attribute attached.

This issue is fixed in ISE 8.1i Service Pack 3.

AR# 22473
日期 11/17/2008
状态 Archive
Type 综合文章
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