We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22492

11.1 MAP - Controlling IOB register packing when register is eligible for both an input and output pack


I have a register that I want to pack into an IOB. The register can be packed into an input and an output IOB. How do I control which IOB is used for the register packing? I tried unsuccessfully to use the MAP switch -pr i|o. Why did this option not work? How do I control which IOB is used?


Most synthesis tools generate IOB registers with IOB=TRUE attributes. This attribute takes precedence over the -pr switch. Consequently, when the IOB attribute is present (TRUE or FALSE), the -pr switch has no effect on that register.

You can use the following MAP packing constraints to control IOB register packing:
- If the target IOB is locked, add a LOC constraint to the register that is the same as the LOC on the pad net or pad that is in the targeted IOB. This forces the register to be packed into the targeted IOB.
- If the IOB is not locked, add the same BLKNM constraint to both the register and pad that is targeted to the IOB. This forces the register to be packed into the targeted IOB.
- Add a KEEP property (or NOMERGE) to control packing. A KEEP on either the input or output net of the register forces the IOB into the output or input IOB, respectively, because the net must remain external to the IOB. This is only true for the input net if there is no other fanout because the IOB could still be packed on the input side without entirely merging the input net into the IOB.
AR# 22492
日期 03/08/2013
状态 Active
Type 综合文章
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less