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AR# 22504

XST - How can I make my "include" file from the top level visible in the submodule?

描述

How can I make my "include" file from the top level visible in the submodule?

解决方案


It is not possible to make the "include" file from your top level visible in the submodule because FPGA synthesis tools perform a bottom-up compilation.

For this reason, it is best to place the "include" in the lowest module of your design, as this will ensure that it will be propagated to the top level as well.

In Project Navigator there is also an option to include the Verilog file globally.
AR# 22504
日期 12/15/2012
状态 Active
Type 综合文章
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