How do I modify the ISE generated testbench to perform an XPS simulation in an ISE environment?
Or, if I create a custom testbench, what additional information should be added to include the block RAM initialization and configuration contents?
Create the testbench in the ISE tool as follows:
- Select the Project pull-down menu > New Source...
- Select VHDL Test Bench.
- Fill in the testbench name in the data entry field.
- Click Next.
- Select the top level VHDL file (system_stub by default).
- Click Next, then Finish.
Modify the newly created testbench:
- Add a configuration design unit between the ENTITY and the ARCHITECTURE for the top level VHDL file (system_stub by default):
ENTITY system_stub_tb_vhd IS
configuration system_stub_conf of system_stub is
for system_i : system
use configuration work.system_conf;
ARCHITECTURE behavior OF system_stub_tb_vhd IS
- Instantiate the system_stub_conf in the newly created testbench file instead of the top level VHDL file (system_stub by default):
uut: configuration work.system_stub_conf PORT MAP(
fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin,
- Because the instantiation of the configuration design unit used direct instantiation, a component declaration is not needed, so comment out the component declaration of the top level VHDL file (system_stub by default).
NOTE: Starting with 12.1, there is an automatic method to include the block RAM initialization that does not require the use of configuration statements.