When instantiating input/output flip flops, FPGA Express (any version up to and including 3.1) gives the following warning message:
"Warning: The pin 'xxxxx/GC' is not connected to any net (FE-CHECK-1)"
This may also occur with instantiated latches and other inferred synchronous logic, and may also refer to a "GS" pin.
This warning can be safely ignored. These warnings refer to the "Global Clear" and "Global Set" pins, which are required for simulation, and have no bearing on synthesis. The fact that they appear in FPGA Express stems from how their libraries were created.