When I run a design with cascaded OSERDES blocks through MAP in 8.1i, I receive the following error.
ERROR:LIT:417 - The OQ pin of OSERDES symbol
"my_design/data_slave" can only be routed to an
OBUF, IOBUF, OBUFDS, OBUTDS, or OFB input of an ISERDES.
Is this a valid error? How do I get past it?
CR 217183 added a logical DRC check in 8.1i that will error out if the OQ pin of an OSERDES symbol does not drive a OBUF or similar primitive. This check causes errors in some valid use cases. CR 220488 contains another example of the bogus check.
Another example is implementing Width Expansion as described on page 378 of the Virtex-4 User's Guide:
Two OSERDES symbols are cascaded using the ShiftIn and ShiftOut ports. The master OQ pin drives an OBUF primitive and the slave OQ pin is left dangling. This valid use case now causes an error. A test case showing this is in the appropriate bug cases directory.
Customers will be able to work around this by setting XIL_MAP_SKIP_LOGICAL_DRC.
This error was intended to ensure that the OQ pin was not used to drive logic and produce unroutable connections. It currently triggers an error for the valid use case where a slave OSERDES has the SHIFTOUT pins is connected to the SHIFTIN of the corresponding master OSERDES.
This problem will be fixed in 8.1 Service Pack 1.
Currently, this error can be avoided by setting the environment variable XIL_MAP_SKIP_LOGICAL_DRC.
For general information about setting ISE environment variables, see (Xilinx Answer 11630).