UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
What is required to meet timing with a BSB-based ML410 design containing an OPB_PCI Core?
Added the following to the UCF file for the ML410 with OPB_PCI in the design:
1) Area Groups
PLB2OPB
AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191;
INST "plb2opb" AREA_GROUP = "pblock_plb2opb";
INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb";
INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb";
INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb";
INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb";
OPB2PLB
AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139;
INST "opb2plb" AREA_GROUP = "opb2plb";
OPB_SPI
AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111;
INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom";
2) PCI to OPB constraint (change "FROMTO" constraint from 10 ns to 9.9 ns and add the "datapathonly" keyword)
Here is the exact UCF string user needs to copy and paste upon BSB design:
TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 9900 ps datapathonly;
Notice that BSB delivers constraint like this:
TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
38093 | ML410 - Known Issues and Release Notes Master Answer Record | N/A | N/A |
AR# 22677 | |
---|---|
日期 | 05/19/2014 |
状态 | Archive |
Type | 综合文章 |