We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22696

LogiCORE Block Memory Generator v1.1 - Width of address bus displayed on the symbol is incorrect


When customizing the Block Memory Generator Core GUI, I find that the address bus width displayed on the symbol is incorrect.


The correct width of the address bus is shown in the Information Panel on the last page of the GUI. 


This issue will be fixed in the next release.

AR# 22696
日期 05/19/2014
状态 Archive
Type 综合文章