Description

I am coding to infer block RAM; there are unused address lines in my code, and XST issues the following warnings:

"WARNING:Xst:646 - Signal <address_a> is assigned but never used.

WARNING:Xst:647 - Input <address_b> is never used."

Furthermore, XST will infer distributed RAM instead of block RAM. The examples illustrate the inclusion of too many address lines:

Verilog:

module ram1(clk,en,we,addr,di,do);

parameter ADDRESSWIDTH = 5;

parameter DATAWIDTH = 10;

parameter RAMDEPTH = 10;

input clk,en,we;

input [ADDRESSWIDTH-1:0] addr;

input [DATAWIDTH-1:0] di;

output [DATAWIDTH-1:0] do;

reg [DATAWIDTH-1:0] ram [RAMDEPTH-1:0];

reg [ADDRESSWIDTH-1:0] read_addr;

always @(posedge clk)

begin

if (en == 1'b1)

begin

if (we == 1'b1)

ram[addr] <= di;

read_addr <= addr;

end

end

assign do = ram[read_addr];

endmodule

VHDL:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity ram1 is

generic (addresswidth : integer := 5;

datawidth : integer :=10;

ramdepth : integer :=10);

port (di : in std_logic_vector (datawidth - 1 downto 0);

addr : in std_logic_vector (addresswidth - 1 downto 0);

clk : in std_logic;

en : in std_logic;

we : in std_logic;

do : out std_logic_vector(datawidth - 1 downto 0));

end entity;

architecture ram1_arch of ram1 is

type ram_type is array (datawidth - 1 downto 0) of std_logic_vector (ramdepth - 1 downto 0);

signal ram : ram_type;

signal read_addr : std_logic_vector(addresswidth - 1 downto 0);

begin

process (clk)

begin

if clk'event and clk = '1' then

if en = '1' then

if we = '1' then

ram(conv_integer(addr)) <= di;

end if;

read_addr <= addr;

end if;

end if;

end process;

do <= ram(conv_integer(read_addr));

end architecture;

解决方案

To avoid these warnings, trim down the address line in the HDL code to properly reflect the actual addresses that will be used:

Verilog:

module ram1(clk,en,we,addr,di,do);

parameter ADDRESSWIDTH = 4; //address width changed from 5 to 4

parameter DATAWIDTH = 10;

parameter RAMDEPTH = 10;

input clk,en,we;

input [ADDRESSWIDTH-1:0] addr;

input [DATAWIDTH-1:0] di;

output [DATAWIDTH-1:0] do;

reg [DATAWIDTH-1:0] ram [RAMDEPTH-1:0];

reg [ADDRESSWIDTH-1:0] read_addr;

always @(posedge clk)

begin

if (en == 1'b1)

begin

if (we == 1'b1)

ram[addr] <= di;

read_addr <= addr;

end

end

assign do = ram[read_addr];

endmodule

This is has been fixed with the release of ISE 5.2i.

To avoid these warnings, trim down the address line in the HDL code to properly reflect the actual addresses that will be used:

VHDL:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity ram1 is

generic (addresswidth : integer := 4; -- address width changed from 5 to 4

datawidth : integer :=10;

ramdepth : integer :=10);

port (di : in std_logic_vector (datawidth - 1 downto 0);

addr : in std_logic_vector (addresswidth - 1 downto 0);

clk : in std_logic;

en : in std_logic;

we : in std_logic;

do : out std_logic_vector(datawidth - 1 downto 0));

end entity;

architecture ram1_arch of ram1 is

type ram_type is array (datawidth - 1 downto 0) of std_logic_vector (ramdepth - 1 downto 0);

signal ram : ram_type;

signal read_addr : std_logic_vector(addresswidth - 1 downto 0);

begin

process (clk)

begin

if clk'event and clk = '1' then

if en = '1' then

if we = '1' then

ram(conv_integer(addr)) <= di;

end if;

read_addr <= addr;

end if;

end if;

end process;

do <= ram(conv_integer(read_addr));

end architecture;