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AR# 22708

8.1i Virtex-4, DRC - "ERROR:PhysDesignRules:1077- Dangling pins on block ."

描述

When I run a design with cascaded OSERDES blocks through BitGen in 8.1i, the following error occurs:  

 

"ERROR:PhysDesignRules:1077 - Dangling pins on block:<data_master>:<OSERDES_OSERDES>. For DATA_WIDTH settings of 7 8 or 10 an OSERDES with SERDES_TYPE set to MASTER must have SHIFTOUT1 and SHIFTOUT2 connected with SHIFTIN1 and SHIFTIN2 unconnected. For a SLAVE setting SHIFTIN1 and SHIFTIN2 must be connected with SHIFTOUT1 and SHIFTOUT2 unconnected." 

 

I have verified that my OSERDES is connected correctly. Why does this error occur? How do I solve this issue?

解决方案

This error is incorrect. The MASTER must have SHIFTIN1 and SHIFTIN2 connected with SHIFTOUT1 and SHIFTOUT2 unconnected. The SLAVE must have SHIFTOUT1 and SHIFTOUT2 connected with SHIFTIN1 and SHIFTIN2 unconnected.  

 

To work around this issue, follow these steps: 

1. Check your Design Rules Check log (.drc) and ensure that there are no other errors. 

2. Run BitGen without DRC by adding the -d option in your command line. Alternatively, you can deselect "Run Design Rules Checker (DRC)" in the options for Generate Programming File in Project Navigator. 

 

This issue will be fixed in ISE 8.1i Service Pack 2, which is scheduled for release in February 2006.

AR# 22708
日期 05/19/2014
状态 Archive
Type 综合文章
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