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AR# 22709

8.2 System Generator for DSP - Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled?

描述

Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled?

解决方案

You can work around this issue by using the DDS v5.0 block.

AR# 22709
日期 05/19/2014
状态 Archive
Type 综合文章
的页面