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AR# 22724

LogiCORE SPI-4.2 (POS-PHY L4) Lite v3.1 - PAR "WARNING:Place: 119 - Unable to find location." PAR "ERROR:Place:249 - Automatic clock placement failed."


When I implement the SPI-4.2 Lite Core design example (with loopback) targeting Spartan-3 and Spartan-3E, the following warnings and errors occur during PAR:

"WARNING:Place:119 - Unable to find location. SLICEL component

core_pl4_lite_snk_top0/U0/pl4_lite_snk_synchronizer0/snk_bus_err/d3 not placed.

SLICEL "core_pl4_lite_snk_top0/U0/pl4_lite_snk_synchronizer0/snk_bus_err/d3".

<COMPGRP "AG_pl4_lite_snk.SLICE" LOCATE = SITE "SLICE_X0Y48:SLIC...> [.\mapped.pcf(2935)] "COMPGRP

"AG_pl4_lite_snk.SLICE" LOCATE = SITE "SLICE_X0Y48:SLICE_X19Y79" LEVEL 4"

The AREA group contains 640 possible sites for this component. 0 of these sites were available to place this component into.


List of comps in area without same LOC are:


WARNING:Place:119 - Unable to find location. SLICEL component

core_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/RSClkRdy_shift<1> not placed.

SLICEL "core_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/RSClkRdy_shift<1>".


ERROR:Place:249 - Automatic clock placement failed. Please attempt to analyze the Global clocking required for this

design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may

be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that

only one clock output signal for any Primary / Secondary pair of clocks may enter any region. For further

information see the "Using Global Clock Networks" section in the V-II User Guide (Chapter 2: Design Considerations)"


This issue has been fixed in SPI-4.2 Lite v4.1 Core released with ISE8.2i IP Update #1. Please upgrade to the latest core. If upgrading is not possible, please use following method to work around this issue.

These errors and warnings occur because the defined area group constraint is too tight to fit all of the components. To remove this error, edit the UCF constraint file and increase the size of the area group in the X direction by 6 spaces.

For example:

Look for following line in the UCF file:

AREA_GROUP "AG_pl4_lite_snk" RANGE = SLICE_X0Y119:SLICE_X45Y60 ;

change to:

AREA_GROUP "AG_pl4_lite_snk" RANGE = SLICE_X0Y119:SLICE_X51Y60 ;

(increasing the upper boundary of the X column from 45 to 51.)

You will need to increase the area for "AG_pl4_lite_src" as well, if it is failing.

AR# 22724
日期 12/15/2012
状态 Active
Type 综合文章