You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
8.1i Floorplanner/PACE - BRAM/MULT locations all show the same location value
Keywords: 8.1, Floor, planner, PACE, BRAM, MULT
In PACE and Floorplanner, the LOC constraints for every placement of a MULT/BRAM results in the same location value. Why is this?
Looking at the part in FPGA Editor reveals that the locations are correct (e.g., X0_Y0 - X1_Y15).