Why does the following DRC error occur in BitGen when RSDS_25 and LVCMOS25 outputs are placed in the same bank:
"ERROR:PhysDesignRules:759 - IOB comp <xx> at location <yy> is incompatible for bank <#>. The incompatible code is <1>."
Putting an LVCMOS25 output in the same bank as an RSDS_25 output is a valid placement.
This problem has been fixed in the latest 8.1i Service Pack available at:
The first service pack containing the fix is 8.1i Service Pack 2.
For more information on banking rules for Spartan-3, see the Functional Description module of the Spartan-3 data sheet located at: