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AR# 22753

8.2i XST - XST generates incorrect logic for VHDL code that assigns a bus bit-by-bit

描述

XST generates incorrect logic for VHDL code that assigns a bus bit-by-bit. An example of the incorrect logic is as follows:

output2 <= "001" when sel = '0' else (0 => input(0), others => '0');

output3 <= input when sel = '1' else (1 => input(1), 0 => input(0), 2 => input(2))

解决方案

XST cannot correctly process the code the way it is written. You can work around this problem by concatenating the bits as shown below:

output2 <= "001" when sel = '0' else ("00" & input(0)) ;

output3 <= input when sel = '1' else ( input(2)&input(1)&input(0));

Xilinx is investigating this issue; look for this to be fixed in ISE 9.1i.

AR# 22753
日期 12/15/2012
状态 Active
Type 综合文章
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