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AR# 22920

Virtex-4 XtremeDSP Slice - There is no per-pin timing information in the data sheet for delay through the DSP48 multiplier as there was in the Virtex-II/Pro data sheet


When I look at the DC and Switching Characteristics in the Virtex-4 data sheet, I only see one value for the combinatorial delay through the XtremeDSP Slice (DSP48); however, for the MULT18X18 in the Virtex-II/Pro data sheet, timing information is available for each pin on the primitive. Why is there a difference in the data sheets?


There is no per-bit characterization for the DSP48 multiplier outputs. Virtex-II/Pro devices are faster for small multipliers because the bottom 12 bits are on one side of the final adder and before the pipeline register, while the upper 24 bits are on the other side of the final adder and after the pipeline register.

The XtremeDSP Slice (DSP48) has a different architecture than Virtex-II/Pro devices. The final adder of the multiplier is in the second stage of the XtremeDSP Slice (DSP48). This is because there is a three-input adder with two of the adder inputs of the adder being used to add the two 36-bit partial products generated in the first stage.

The second stage 48-bit adder is designed for 500MHz for all 48 bits, and it is vastly different than the adder used in Virtex-II/Pro devices. The bottom few LSBs do exit a few pico-seconds faster; but overall, the adder outputs exit at the same time due to new adder IP. Thus there is no reason to add per-bit characterization.

AR# 22920
日期 12/15/2012
状态 Active
Type 综合文章