My design has an ODDR2 driving an IOBUFDS. When I perform behavioral simulation, I see the behavior that I expect on the outputs. In timing simulation and hardware, I see the master and slave pads both putting out the same signals instead of the inverse of each other. Why is this occurring?
This issue will be fixed in 8.1i SP3.
In the meantime, to work around the problem, edit the design in FPGA Editor and manually invert the slave signals inside the IOB.
It is also possible to create an FPGA Editor script to automate this process and correct multiple occurrences.