AR# 230: 94 DATA BOOK 2nd: Presettable Down Counter on page 8-72 is misdrawn
94 DATA BOOK 2nd: Presettable Down Counter on page 8-72 is misdrawn
The figure "Presettable Down Counter" is misdrawn. The AND gate below T5 in the upper-right-hand corner of the drawing calculates whether bits 1-4 of the counter are low. This is passed on to the T6 AND gate, and this gate is supposed to make T6 active (high) when bits 5-0 of the counter are all low, and similarly for T7 and bits 6-0 of the counter. However, the schematic as drawn makes T6 high whenever bits 5 and 0 are low *and* at least one of bits 1-4 is high! Similarly, T7 is high whenever bits 6, 5, and 0 are low *and* at least one of bits 1-4 is high. This also messes up the terminal count.
Fixing this can be accomplished in one of two ways:
1. Removing the second bubble down off the T6 and T7 AND gates, and the first bubble down on the AND gate feeding the terminal-count flip-flop.
2. Placing a bubble on the output of the AND gate below T5.
The second solution was implemented in the 94 data book 3rd edition