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AR# 23035

8.1i FPGA Editor - Editing components cause BitGen to fail with DRC errors

描述

When I edit a component in the FPGA Editor, and use the trim command as described in (Xilinx Answer 21667), the resulting configuration causes many DRC errors similar to the following:

"ERROR:PhysDesignRules:368 - The signal <u_dcm/u_dcm.PSCLK> is incomplete. The signal is not driven by any source pin in the design."

or

"ERROR:PhysDesignRules:368 - The signal <MGT0.BREFCLK> is incomplete. The signal is not driven by any source pin in the design."

解决方案

This will be fixed in 8.1i Service Pack 3.

AR# 23035
日期 12/15/2012
状态 Active
Type 综合文章
的页面