Why do I get all zeros on my output in my post-MAP or post-PAR HDL simulation, while behavioral and post-translate HDL simulations are fine?
This is due to a known bug in System Generator. System Generator fails to find an appropriate clock signal for simulation purposes in a generated HDL file. The problem is indicated in Xilinx SimPrim/UniSim blocks with a clock pin driven by a steady state source, which can occur with zero latency DSP48 blocks, multipliers etc. You can currently work around the problem by adding latency to the DSP48 blocks (or other affected blocks) in your design.
This will be fixed in System Generator for DSP 8.2, scheduled for release in July 2006.