We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 23298

Virtex-4 ISERDES/OSERDES - RST recovery and removal time are not included in the data sheet or analyzed by the Timing Analyzer tool


Keywords: reset

The asynchronous reset signal for the Virtex-4 ISERDES and OSERDES should have an associated recovery and removal time with respect to the CLKDIV signal. I cannot find this parameter in the Virtex-4 data sheet, and this relationship is not analyzed by the Timing Analyzer tool.


This timing is currently not documented in the Virtex-4 data sheet. Also, the Timing Analyzer tools do not currently support recovery and removal analysis.

Xilinx recommends that the RST signal be synchronized in the ISERDES or OSERDES CLK or CLKDIV domain to avoid any violation of the recovery or removal times.

Support of recovery and removal analysis will be included in the 9.1i Timing Analyzer software.
AR# 23298
日期 05/22/2006
状态 Active
Type ??????