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AR# 2339

12.1 Known Issue Timing Constraint CPLD - The Timing Ignore (TIG) constraint is not supported

Description

The CPLD fitter software does not support the TIG constraint. If my UCF file includes the TIG constraint, the optimizer generates the following warning:

"WARNING:hi607 - Ignoring MAXDELAY:FROM:POINTA:TO:POINTB:TIG.
CPLD designs do not support point-based specifications such as TPSYNC, TPTHRU, TIG and IGNORE."

What can I use instead of TIG?

解决方案

To set a TIMESPEC that ignores a particular path, you must create separate TIMESPECs for the paths that you want to constrain.

For example, if you want a 100 ns delay on all flip-flop paths in the design except from POINTA to POINTB, you might try to use the following TIG constraint to ignore one particular path:

TIMESPEC TS01=FROM:FFS:TO:FFS:100;
TIMESPEC TS02=FROM:POINTA:TO:POINTB:TIG;

However, you must modify this code so that all flip-flops except POINTA and POINTB have another TNM, such as REAL_PATH, associated with them. You can now TIMESPEC only REAL_PATH:

TIMESPEC TS01=FROM:REAL_PATH:TO:REAL_PATH:100;

AR# 2339
创建日期 08/21/2007
Last Updated 05/03/2010
状态 Active
Type 已知问题
器件
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  • 9500XL
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