The CPLD fitter software does not support the TIG constraint. If my UCF file includes the TIG constraint, the optimizer generates the following warning:
"WARNING:hi607 - Ignoring MAXDELAY:FROM:POINTA:TO:POINTB:TIG.
CPLD designs do not support point-based specifications such as TPSYNC, TPTHRU, TIG and IGNORE."
What can I use instead of TIG?
To set a TIMESPEC that ignores a particular path, you must create separate TIMESPECs for the paths that you want to constrain.
For example, if you want a 100 ns delay on all flip-flop paths in the design except from POINTA to POINTB, you might try to use the following TIG constraint to ignore one particular path:
However, you must modify this code so that all flip-flops except POINTA and POINTB have another TNM, such as REAL_PATH, associated with them. You can now TIMESPEC only REAL_PATH: