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AR# 23421

8.2i Floorplan Editor Virtex-4/-5 - Unable to lock (LOC) placement of global logic components (RAM, PPC, DCM, etc.)


Using the Floorplan tab or the Package tab after launching Assign Area Constraints or Assign Package Pins, I cannot lock down my global logic (block RAM, PPC, DCM, etc.) with the distribution button set to distribute right, left, up, or down. Once they are placed, I cannot move them without deleting them first. I also cannot see several types of device resources (BUFR, BUFIO, IDELAYCTRL, GTP_BUAL, PCIE, TEMAC, etc.) that I would like to lock down.


To work around this issue, place the elements one at a time or create the constraints manually in a text editor.

Another way to work around this issue is with the Design Objects tab. You can set the filter to ALL and manually enter the location to place the components.

This problem has been fixed in the latest 8.2i Service Pack available at:

The first service pack containing the fix is 8.2i Service Pack 2.

AR# 23421
日期 01/18/2010
状态 Archive
Type 综合文章