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AR# 23448

10.1 XST - "ERROR:HDLCompilers:87 - "<Verilog file name>" line <###> Could not find module/primitive <module name>'"


Keywords: HDL, compilers, 87, error, ifdef, include, define, remote, Tcl, xfile, Project Navigator

The following error occurs when synthesizing a Verilog design:

"ERROR:HDLCompilers:87 - "<Verilog file name>" line <###> Could not find module/primitive <module name>'"


"ERROR:HDLCompilers:87 - "my_verilog.v" line 129 Could not find module/primitive my_mod1'"



This error can be caused by a Project Navigator specific problem where the HDL files loaded in the project refer to definitions in other HDL files that are not explicitly included in the design.

A design can use Verilog "include" statements to control how the design is elaborated or parsed. For instance, an "iinclude" is for "defines", and then the "defines" either enable or disable the instantiation of a module.


my_mod1 #(`PNAME1,`PNAME0) my_mod2

Where PNAME1 and PNAME0 are defined in a file that does not reside in the current working directory.

The current working directory (the directory where the .ise file is located) is the only place where XST searches for an 'include file unless it is passed a Verilog include path. If the include file is in another directory, it is not found and Project Navigator does not recognize the 'ifdefs correctly. When the design is synthesized, the missing headers cause an error message.

There are three possible ways to work around this issue:
- Move the included files to the "project" directory (where the .ise file resides). Then touch all the files in the design that use the includes and it should update the hierarchy correctly. If not, remove and re-add the files.
- You can specify the path to the included file relative to the project directory.
- The Verilog include path property in Project Navigator (in the synthesis and simulation options), can be used to set a path to find the includes, as follows:

1. Select the top level file in the Sources window.
2. Right-click on the XST process and select properties.
3. Look for the property "Verilog Include Directories". Set the property to the directory where the defines file is located. Make sure the Property display level is set to Advanced (not Standard). Select Advanced if necessary.
4. Select OK.

NOTE: Command line users will most likely not experience this issue since they will be adding the header file to their compile list. Project Navigator does not allow you to add the include file to the project.


In ISE 10.1, this error message occurs if Verilog files from a remote directory are added with the "xfile add" Tcl command. The Verilog "include" directory setting passed to XST from Project Navigator is not getting updated until the project is closed and opened again.

This error can also occur if you are incorrectly instantiating a black box module. Please refer to the "Black Boxes Coding Examples" of the XST guide. http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf
AR# 23448
日期 02/26/2009
状态 Active
Type 综合文章