In simulation, RXRECCLK does not lock to the correct frequency unless there is data present on the RX serial pins.
The problem occurs only in simulation when the Analog CDR is being used and there is no data present on the RXP and RXN pins.
This will not be a problem in actual silicon because in the absence of data, the CDR will lock to the reference clock.
The SmartModel is fixed in 8.2.01i software. A patch is available for 8.1i tools, see (Xilinx Answer 23472).