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AR# 23515

8.2i MAP - Detailed explanation of the Virtex-5 MAP Design Summary


The Design Summary section of the Virtex-5 MAP report has been updated to reflect the changes in this architecture. This Answer Record provides an explanation of the entries in this summary.


The Design Summary section of the MAP report (.mrp) lists the hardware elements used by the design. A resource is only listed in this summary if it is used at least once in the design.

Slice Logic Utilization

This section of the report lists registers by type (flip-flop vs. latch) and the LUT usage by type (logic vs. memory). The LUT usage is further divided into usage for O5 outputs only, O6 outputs only, or both O5 and O6 used on a per-LUT basis. The memory usage is divided first by type (Dual Port RAM, Single Port RAM, and Shift Register), and then by output pin usage (O5, O6, or both).

Each Virtex-5 LUT has six independent inputs and two independent outputs. Depending on the functions implemented in the LUT, the O5, O6, or both outputs can be used. If both outputs are used, the LUT is completely utilized and no other logic can be added. If the O6 output only is used, it is possible to add another logic function of up to five of the inputs if they are shared. If the O5 output only is used, the LUT is only half full and can share any other five input functions that share the inputs. Consult the "CLB Overview" section of the Virtex-5 User Guide for more details on the many configuration and connection possibilities of the Virtex-5 LUT.

Route-thrus and Latch-thrus

Occasionally, LUTs or Latches must be used to access internal slice resources such as registers, muxes, or carry logic. This usually occurs when dedicated access points are already used within a slice. The number of Route-thrus and Latch-thrus are reported in the Slice Utilization section. Latch-thrus are grouped with the Register counts. Route-thrus are listed after the LUT information, and are further broken down by their O5 and O6 pin usage. Latch-thrus are discussed in more detail in (Xilinx Answer 23267) Route-thrus are discussed in more detail in (Xilinx Answer 23871) Logic Distribution

A new entry in the Device Summary is the list of LUT-Flop pairs used in your design. Since each slice contains four six-input LUTs and four flip-flops, each Virtex-5 slice can contain more than twice the amount of logic than previous architectures. Instead of listing the number of occupied slices (which could make it appear that the device is much fuller than it is), density numbers are reported by showing each linked pair of LUTs and storage elements as partially or fully used.

"Either LUT or Flip-Flop pair used" represents the case in which either of the two sites, or both, are used. "Both LUT and Flip-Flop pair used" represents the case in which both sites are used. You can use these numbers to further calculate other information. For example, subtract the number of "Both" from the total Slice Flip-Flops to see how many registers are placed without a LUT driving it directly; similarly subtract the number of "Both" from the total Slice LUTs to see how many LUTs do not directly drive a register. You can also determine the percentage of Flip-Flops driven directly from LUTs by dividing the number of "both" into the number of Slice LUTs. Use all of these numbers to obtain an accurate indication of how many resources are still available within the device.

I/O Utilization

This section reports the number of bonded and unbonded (if used) I/O pins in the device.

Special Feature Utilization

This section lists all of the remaining components used in your design, including block RAMs, FIFOs, global clocks, and hard IP elements. Clocking resources include BUFG/BUFGCTRL, BUFIO, and BUFR, as well as DCM_ADV and PLL_ADV. Hard IP elements range from Boundary Scan (BSCAN) and STARTUP blocks to the DSP48E resources.

The total number of block RAM resources used is listed first, followed by a breakdown of the total number of 36K and 18K block RAM and FIFO primitives used. Since each block RAM resource can contain either one 36K element or two 18K elements, the total number of 36K and 18K counts can exceed the total number of resources used. The total memory used represents the maximum amount of memory possible set aside by the consumed resources, and not the amount utilized by the specific connectivity of the design. For example, a 128x18 RAM and a 512x14 RAM each "consume" 18K of block RAM, since they require one half of a RAMB36 resource to implement.

For more information on the dedicated features of the Virtex-5 architecture, consult the Virtex-5 User Guide at:


AR# 23515
日期 12/15/2012
状态 Active
Type 综合文章