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CPLD timing constraints are a subset of those supported by FPGAs.
This Answer Record contains a list of constraints currently unsupported by CPLD implementation tools.
Offsets that:
- specify a timegroup
- specify HIGH/LOW
Period that:
- specifies a non 50/50 duty cycle
- mixes register polarity
- does not trace to CE
False Paths/ TIG:
- Does not work
See (Xilinx Answer 2339).
"Through" paths/ TPTHRU
- Does not work
FROM To
- That uses * or / in syntax
TNM:
TNM for CPLDs should only be placed on a Net, not on Instances or Pins.
Examples of valid constraints are :
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
OFFSET = IN 5 ns BEFORE "clk";
OFFSET = OUT 5 ns AFTER "clk";
NET "clk" BUFG=CLK;
TIMESPEC "TS_pads2pads"=FROM PADS TO PADS 6 ns;
For further information on CPLD timing, please See (Application Note XAPP1047)
AR# 23562 | |
---|---|
日期 | 12/15/2012 |
状态 | Active |
Type | 综合文章 |