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AR# 2379

SYNPLIFY - How do I lock down I/O pins in HDL using XC_LOC (Verilog/VHDL)?

Description

Keywords: Verilog, VHDL, Synplify, I/O pin, Synplicity, LOC

Urgency: Standard

General Description:
How do I lock down I/O pins in HDL using Synplicity's Synplify?

解决方案

1

Assigning I/O locations into HDL -- VHDL code

library IEEE;
use IEEE.std_logic_1164.all;

entity iob_loc_ex is
port (CLK : in STD_LOGIC;
A, B : in STD_LOGIC_VECTOR (3 downto 0);
O : out STD_LOGIC_VECTOR (3 downto 0));

attribute xc_loc : string;
attribute xc_loc of CLK : signal is "P13";
attribute xc_loc of A : signal is "P19,P20,P23,P24";
attribute xc_loc of B : signal is "P25,P26,P27,P28";
attribute xc_loc of O : signal is "P48,P49,P50,P51";
end iob_loc_ex;

architecture xilinx of iob_loc_ex is

signal Q : STD_LOGIC_VECTOR (3 downto 0);

begin
U0: process (CLK)
begin
if (CLK'event and CLK='1') then
Q <= A;
end if;
end process;

-- Insert user's application here
O <= Q and B;

end xilinx;

2

SDC
Vendor-specific constraints are passed in an .sdc file.

define_attribute CLK xc_loc "P13"
define_attribute {A[3:0]} xc_loc "P19,P20,P23,P24"
define_attribute {B[3:0]} xc_loc "P25,P26,P27,P28"
define_attribute {O[3:0]} xc_loc "P48,P49,P50,P51"

3

Assigning I/O locations into HDL -- Verilog code

module iob_loc_ex (CLK, A, B, O);
input CLK /* synthesis xc_loc="P13" */;
input [3:0] A /* synthesis xc_loc="P19,P20,P23,P24" */;
input [3:0] B /* synthesis xc_loc="P25,P26,P27,P28" */;
output [3:0] O /* synthesis xc_loc="P48,P49,P50,P51" */;

reg [3:0] Q;

always @ (posedge CLK)
begin
Q <= A;
end

// token logic
assign O = Q & B;

endmodule

4

NOTE: In Synplify/Synplify Pro, the LOC constraints are written in to the NCF file. Please be sure to include the NCF file in your XILINX implementation project directory to ensure the correct annotation.

ALSO NOTE: Synplify's XC_LOC will be written in to the EDIF netlist. As the "xc_loc" attribute is a Synplify-only constraint, the implementation tools will safely ignore it.

- Please see (Xilinx Answer 8055) for an example of LOC/RLOC-ing instantiated Xilinx primitives into CLB.
AR# 2379
创建日期 06/09/1997
Last Updated 04/24/2007
状态 Archive
Type 综合文章