This Answer Record applies only to Virtex-4 and Virtex-5 FPGA. Virtex-6 FPGA does not support the "Insert IDELAY on RDClk" feature for Global Clocking.
This is an issue only when the Sink Core uses Global Clocking and the DPA Clock Adjustment option along with the "Insert IDELAY on RDClk" option. When PhaseAlignRequest is asserted, the IDELAY goes through the reset process and the clock stops toggling momentarily. This causes the DCM to lose lock. In addition, the DPA logic shifts the clock using the IDELAY primitive, and this action might cause the Locked_RDClk lock signal from the DCM to de-assert, or the DcmLost_RDClk signal to assert. To avoid issues with core operation, momentary de-assertions of Locked_RDClk and momentary assertions DcmLost_RDClk signals should be ignored after PhaseAlignRequest has been asserted.
09/21/2006 - Initial Release
06/24/2009 - Updated with Virtex-6 FPGA information
10/27/2011 - Update issue description