AR# 2411: COREGEN: Latency of the 4K Area-Optimized Multiplier core
AR# 2411
COREGEN: Latency of the 4K Area-Optimized Multiplier core
描述
General Description:
The variable multiplier is pipelined several times in order to enable it to run at high frequencies. The latency that results from pipelining is a function of the width of the B input.
解决方案
The Data is buffered on the input and output of the multiplier cores. The total latency (number of clocks required to get the first output) is a function of the width of the B variable only. The values below presume that both inputs and outputs are registered.
Width of B input data Latency (# of clocks)
6 to 8 bits 4 clocks 9 to 16 bits 5 clocks 17 to 32 bits 6 clocks