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AR# 2415

FPGA Express v1.2: LogiBLOX in the FPGA Express v1.2 Verilog or VHDL M1.3 Flow

Description

Keywords: FPGA, Express, 1.1, 1.2, LogiBLOX, black box, black-box,
instantiation, RAM, ROM

Urgency: hot

general description:

It is possible to use LogiBLOX in the FPGA Express v1.x VHDL flow in M1.
In general, there is no real reason to use LogiBLOX, since the desired logic
can be described in the user's VHDL code with one exception: if the user has
to create blocks of RAM or ROM.

解决方案

1

How to instantiate LogiBLOX in the FPGA Express v1.2 M1.3 VHDL Flow

(1) First, run LogiBLOX and, at a minimum, make sure that the
.ngo, and .vhi (VHDL template file) are created. When using
LogiBLOX, select 'Synopsys' as the vendor and use the default
bus notation.

(2) In the .vhi file, take the component declaration of the
LogiBLOX module and place it in the 'architecture' where the
LogiBLOX will be instantiated; this component declaration must
be inside the architecture before the 'begin' line in the
'architecture.'

(3) In the .vhi file, take the component instantiation and
place it after the 'begin' line in the architecture from step
(2); in the component instantiation, you will need to add the
names of the ports/signals that connect to the LogiBLOX pins.

(4) Repeat steps (2) and (3) for any other LogiBLOX components
you need to instantiate in your VHDL code.

(5) Create a project within FPGA Express and analyze all the
.vhd files.

(6) After the analysis of the VHDL files is complete,
implement the design.

(7) After implementing the design, double-click on the
implementation and select the 'modules' tab. This will list
all the components in your design, including the instantiated
LogiBLOX. The instantiated LogiBLOX will be reported as
'UNLINKED'.

Preserve this module by clicking on the cell adjacent to the
'unlinked' LogiBLOX module. A drop-down menu will appear.
Select preserve. Do this for any other LogiBLOX modules in
your design. Save the implementation changes.

(8) Optimize the design in FPGA Express and then write out the
.XNF file.

(9) Check the .XNF file produced by FPGA Express. Make sure
that there exists a SYM record for each and every instantiated
LogiBLOX module in your design. FPGA Express should not write
out a .XNF file for each LogiBLOX module in your design.

(10) With the .XNF file(s) made by Express (sometimes FPGA
Express writes out XNF files made up of XNF primitives, like
LD_1.XNF), run the M1 core tools to place and route.

2

How to Instantiate LogiBLOX in the FPGA Express v1.2 M1.3
Verilog Flow

(1) First, run LogiBLOX and, at a minimum, make sure that the
.ngo file, and .vei (Verilog template file) are created. When
using LogiBLOX, select 'Synopsys' as the vendor and use the
default bus notation.

(2) In the .vei file, cut-and-paste the instantiation portion
of the .vei file into your Verilog code. Do not use the
module definition of the LogiBLOX module in the .vei file.
Connect the instantiation code from the .vei file to the
reg/wire/ports in your Verilog code.

Repeat this step for every LogiBLOX module that will be used
in your Verilog code.

(3) Create a project in FPGA Express and analyze all the .v
files.

(4) After the analysis of the Verilog files is complete in
FPGA Express, implement the design.

(5) After implementing the design, double-click on the
implementation and select the 'modules' tab. This will list
all the components in your design, including the instantiated
LogiBLOX. The instantiated LogiBLOX components will be
reported as 'UNLINKED'.

Preserve this module by clicking on the cell adjacent to the
'unlinked' LogiBLOX module. A drop-down menu will appear.
Select 'preserve'. Do this for any other LogiBLOX modules
instantiated in your design. Save the implementation changes.

(6) Optimize the design in FPGA Express and then write out the
XNF file.

(7) Check the .XNF file produced by FPGA Express. Make sure
that there exists a SYM record for each and every instantiated
LogiBLOX module in the design. FPGA Express should not write
out a XNF file for each of the LogiBLOX modules in your
design.

(8) With the XNF file(s) made by Express (sometimes FPGA
Express writes out XNF files made up of XNF primitives, like
LD_1.XNF for 4ke latches), run the M1 core tools to place and
route.
AR# 2415
创建日期 06/11/1997
Last Updated 03/19/2000
状态 Archive
Type 综合文章