AR# 24367

Virtex-5 FPGA GTP RocketIO Transceiver - Answer Record List

描述

This Answer Record contains a list of all Xilinx Answer Records pertaining to the Virtex-5 FPGA GTP transceivers.

解决方案

Usage
(Xilinx Answer 25385) - Virtex-5 FPGA GTP RocketIO - Special considerations for aligning commas to the least significant RXDATA byte
(Xilinx Answer 29218) - Virtex-5 FPGA GTP RocketIO transceiver- Loss of Sync (LOS) does not behave as expected in certain conditions
(Xilinx Answer 29257) - Virtex-5 FPGA GTP RocketIO transceiver - SATA OOB/Beacon Signaling - Deviation from UG196 v1.4
(Xilinx Answer 30042) - Virtex-5 FPGA GTP RocketIO transceiver - Clock correction does not occur in unbonded transceivers when CHAN_BOND_MODE = "SLAVE"
(Xilinx Answer 31251) - Virtex-5 FPGA GTP RocketIO Transceiver Pipelining
(Xilinx Answer 31283) - Virtex-5 FPGA GTP RocketIO Transceiver - Spread-Spectrum Clocking Limitations
(Xilinx Answer 31508) - Virtex-5 FPGA GTP RocketIO Transceiver - TXKERR and TXRUNDISP meaning for a 2-byte interface
(Xilinx Answer 31589) - Virtex-5 FPGA GTP RocketIO Transceiver - RXELECIDLE usage while in Near-end PMA loopback
(Xilinx Answer 31789) - Virtex-5 FPGA RocketIO Transceiver GTP - Reserving routing for advanced reference clock routing
(Xilinx Answer 31791) - Virtex-5 FPGA RocketIO Transceiver GTP - RXP/RXN recommendations in an unused tile
(Xilinx Answer 31987) - Virtex-5 FPGA GTX/GTP RocketIO Transceiver - Disparity Errors at near-end interface when using Far-end PCS Loopback
(Xilinx Answer 31791) - Virtex-5 FPGA GTP RocketIO Transceiver- Unused GTP power guidelines when forwarding a clock
(Xilinx Answer 33473) - Virtex-5 FPGA GTP RocketIO Transceiver - Instantiating an unused GTP to forward reference clocks

Simulation
(Xilinx Answer 30300) - Virtex-5 FPGA GTP RocketIO Transceiver - The TXN and TXP ports are undefined in simulation
(Xilinx Answer 31423) - Virtex-5 FPGA GTP/GTX RocketIO Transceiver- SIM_MODE attribute description
(Xilinx Answer 31781) - Virtex-5 FPGA RocketIO Transceiver GTP - DRP reads PCS_COM_CFG incorrectly in simulation

CRC Block
(Xilinx Answer 29143) - Virtex-5 FPGA RocketIO Transceiver GTP - Common issues with the CRC block
(Xilinx Answer 24879) - Virtex-5 FPGA RocketIO Transceiver GTP - CRC Errata Clarification

Board Level Considerations
(Xilinx Answer 29766) - Virtex-5 FPGA RocketIO Transceiver GTP - Grounding the GTP power supplies will cause BSCAN testing to fail
(Xilinx Answer 30915) - Virtex-5 FPGA GTP RocketIO Transceiver - MGTAVCC Power recommendations for unused tiles between calibration resistor and instantiated tiles
(Xilinx Answer 38410) -Virtex-5 FPGA GTP/GTX Transceiver: What is the RX impedance value before and after power up and configuration?

Software Version Specific Considerations
(Xilinx Answer 24533) - Virtex-5 LXT RocketIO Transceiver- RX termination for GTP0 and GTP1 are swapped in ISE Design Suite 9.1.01i and earlier
(Xilinx Answer 25110) - Virtex-5 LXT/SXT FPGA RocketIO Transceiver- Comma Alignment block behavior in ES vs. Production silicon
(Xilinx Answer 25111) - Virtex-5 FPGA GTP RocketIO - 9.1 Certain attributes must be set in the UCF file
(Xilinx Answer 29128) - Virtex-5 FPGA RocketIO Transceiver GTP - Designs show timing failures on CHBONDO / CHBONDI ports in ISE 9.2.01
(Xilinx Answer 29171) - Virtex-5 FPGA GTP RocketIO Transceiver - GTP timing simulations fail in ISE Design Suite 9.2.02
AR# 24367
日期 08/30/2012
状态 Active
Type 综合文章
器件 More Less
IP