Synthesizing a Verilog design which instantiates an IP core yields the following error:
"ERROR:HDLCompilers:87 - "<Verilog file name>.vline <###> Could not find module/primitive '<IP core name>'"
"ERROR:HDLCompilers:87 - "stopwatch.v" line 41 Could not find module/primitive 'tenths'"
In ISE 9.1i, Project Navigator does not properly handle the support files for IP cores with EDN netlist.
As a method by which to work around this issue, if the IP core supports VHDL, the Functional Model Target Language for the core can be changed to VHDL. To do this, select the IP core in the sources window, then right-click View HDL Functional Model, and select Properties.