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AR# 24603

LogiCORE Endpoint Block Plus v1.2 and v1.2.1 for PCI Express - Release Notes and Known Issues for 9.1i IP Update 1 (9.1i_IP1) and 9.1i IP Update 2 (9.1i_IP2)


This Release Note and Known Issues Answer Record is for the LogiCORE Endpoint Block Plus v1.2 for PCI Express released in 9.1i IP Update 1, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 24307).


General Information

Patch Update

IMPORTANT NOTE: 9.1i IP Update 2 is a cumulative IP Update release. However, the LogiCORE Endpoint v1.2 for PCI Express was not updated in IP Update 2. Consequently, the same core exists in both IP Update 1 and IP Update 2. As a result, if you have installed the v1.2.1 patch, you must reinstall it after installing the 9.1i IP Update 2.

A patch update (v1.2.1) is available for the LogiCORE Endpoint Block Plus for PCI Express v1.2. To install this patch, you must first install the 9.1i IP Update 1 CORE Generator update. This must be downloaded and installed on top of the current ISE 9.1i sp2 design tools. For general information on this update, see (Xilinx Answer 24307). This update is found at:


Once the IP Update has been installed, download the patch at:


To install this v1.2.1 patch update, unzip the file into your current Xilinx install directory, as pointed to by your Xilinx environment variable. You might be prompted to allow the update to overwrite existing files; select "Yes to All."

License Requirements

As of the ISE 9.1i sp 2 IP Update 1 release, the LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license. To obtain the license visit the product lounge at:


New Features

- Improved Timing Closure

- Added Completion Streaming Mode

Bug Fixes

- CR 432068: trn_reset_n is not triggered by sys_reset_n

- CR 431681: Reference clock frequency should default to 100 MHz

- CR 429604: BAR4 mismatch between GUI and core

Known Issues

- Refer to the "readme_pcie_blk_plus.txt" file delivered with the core for known issues at the time of the release.

- The LX330T x1, x4, and x8 designs do not meet timing with the default CORE Generator settings. Future versions of ISE design tools will address this issue. There is currently no work-around available.

- Core Receive Flow Control Credit Available signals are unavailable; trn_rfc_{p,np}h_av[7:0] and trn_rfc_{p,np}d_av[11:0] are not indicating correct values. These signals are considered informational only and are not critical for correct operation of Endpoint application.

- Warm reset causes core to not respond to memory aperture implemented by the Endpoint. This is fixed in v1.2.1 patch.

- See (Xilinx Answer 24174) if you receive an error stating "ERROR:coreutil - Failure to generate output products" in CORE Generator.

- (Xilinx Answer 24887) Library mappings not found when running example design.


AR# 24603
日期 12/15/2012
状态 Active
Type 综合文章