AR# 24860

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LogiCORE Block Memory Generator v2.4 - BitGen "ERROR:PhysDesignRules:1530 - Dangling pins on block:../blk_mem_generator/SP.CASCADED_PRIM36.."

描述

When running implementation on a design containing Block Memory Generator Core, configured in Single Port RAM or ROM, the following BITGEN error can occur:

"Running DRC.

ERROR:PhysDesignRules:1530 - Dangling pins on

block:<inst1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SP.C

ASCADED_PRIM36.TDP_T/inst1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram

.r/v5.ram/SP.CASCADED_PRIM36.TDP_T>:<RAMB36_EXP_RAMB36_EXP>. Port B with

attribute RAM_EXTENSION_B set to UPPER requires CASCADE input pin connected.

ERROR:PhysDesignRules:1532 - Dangling pins on

block:<inst1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SP.C

ASCADED_PRIM36.TDP_B/inst1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram

.r/v5.ram/SP.CASCADED_PRIM36.TDP_B>:<RAMB36_EXP_RAMB36_EXP>. Port B with

attribute RAM_EXTENSION_A set to LOWER requires CASCADE output pin connected.

ERROR:Bitgen:25 - DRC detected 2 errors and 0 warnings."

解决方案

When building any deep Single Port RAM or Single Port ROM, with greater than 24K deep and with write and read ports which are the same width, the cascaded 32kx1 primitive (Virtex-4) or cascaded 64kx1 primitive (Virtex-5) will be used. However, the cascade in/out pins for port B are not connected (since it is a single port RAM/ROM, port B is not used). The BitGen DRC checks fail because of this issue.

To work around this issue, generate a True Dual Port RAM and tie-off unused ports.

This issue will be fixed in Block Memory Generator V2.5, delivered with IP Update #3 scheduled for May of 2007.

AR# 24860
日期 12/15/2012
状态 Active
Type 综合文章
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