Intermittent failures with ZBT memory are attributed to a non-optimal signal integrity on sram_clk pin in the UCF file.
Update the ML505 UCF as follows:
Change NET sram_clk IOSTANDARD as follows:
NET sram_clk IOSTANDARD = LVDCI33 ;
NET sram_clk IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;
NOTE: For other ML505 board issues, perform an Answer Record search for ML505.
This problem has been fixed in the latest EDK 9.1i Service Pack, available at:
The first service pack containing the fix is EDK 9.1i Service Pack 1.