UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 24955

ML505 - ML505 ZBT SRAM clock signal integrity issue

描述

Intermittent failures with ZBT memory are attributed to a non-optimal signal integrity on sram_clk pin in the UCF file.

解决方案

Update the ML505 UCF as follows:

Change NET sram_clk IOSTANDARD as follows:

From:

NET sram_clk IOSTANDARD = LVDCI33 ;

To:

NET sram_clk IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST;

NOTE: For other ML505 board issues, perform an Answer Record search for ML505.

This problem has been fixed in the latest EDK 9.1i Service Pack, available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 9.1i Service Pack 1.

AR# 24955
日期 12/15/2012
状态 Active
Type 综合文章
的页面