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AR# 25271

MIG v1.72 - Virtex-4 DDR2 SDRAM Direct Clocking design requires user interface enable, data, and data mask signals to be held low until initialization completes


Keywords: Memory, Interface, Controller, APP_AF_WREN, APP_WDF_WREN, APP_WDF_DATA, APP_MASK_DATA, 1.7

The Virtex-4 DDR2 SDRAM Direct clocking design has specific requirements on the user interface signals during initialization/calibration. The testbench module included in the "withtb" design follows these requirements on the user interface signals. However, when the testbench module is removed ("withouttb" design) and the design is connected to the user application, these requirements must be manually followed.


The write data FIFO within the MIG-generated design is used for storing either the data pattern used during calibration or the write data used during normal operation. The data pattern for the calibration is written into the FIFO at start up after reset is deasserted. To reduce resources and help with timing, the FIFO input is driven by the logical OR of the user write data and the data patterns.

Consequently, user interface signals must be held Low to allow the correct calibration pattern to be written into the FIFO. After the calibration, all the signals from the calibration state machine are held Low to allow the user interface values to be written into the FIFO correctly.

The user interface signals that must be held Low are shown below (shown from the top_0.v module level). These signals should all be held Low until the calibration/initialization is complete (assertion of init_done).

input APP_AF_WREN, -- held low until init_done is asserted
input APP_WDF_WREN, -- held low until init_done is asserted
input [(`dq_width*2)-1:0] APP_WDF_DATA, -- held low until init_done is asserted
input [(`dm_width*2)-1:0] APP_MASK_DATA, -- held low until init_done is asserted

output init_done, -- signal will be asserted once initialization is completed
AR# 25271
日期 04/06/2009
状态 Archive
Type 综合文章