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AR# 2533

4.1i NGD2VER - How is the -ne option used to handle escaped names?


Keywords: Verilog, NGD2VER

Urgency: Standard

General Description:
How is the -ne option used to handle escaped names?


The backslash is used as an escape character in Verilog. In the Xilinx ISE release, NGD2VER "escapes" any net or block name containing illegal Verilog characters.

An escaped Verilog name contains a backslash ("\") prefix in front of that name, along with a terminating blank space. For example, the original net name "p1$i40/empty" becomes "\p1$i40/empty " (note the terminating blank space). This happens because the illegal Verilog character "/" is used as a hierarchy designator in the input design.

The Verilog-legal set of characters is limited to the following:

a-z, A-Z, 0-9, _, $ (For more information, please see (Xilinx Answer 1535).

NGD2VER will also escape any reserved Verilog names that are used in a design (e.g., "input", "output", etc.).

Any OVI/IEEE 1364-compliant simulator should accept escaped Verilog names.

The -ne option ("Do not escape names") will replace all invalid Verilog characters (including "/") with the underscore ("_") and, will not escape the name with the backslash. For example,

Without -ne:
wire \d_in3/INBLOCK/I ;

With -ne:
wire d_in3_INBLOCK_I;
AR# 2533
日期 06/13/2002
状态 Archive
Type ??????