We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2546

V1.4.0 CORE Generator: Viewlogic Synthesis Flow (VHDL only)


Keywords: DSP, Coregen, Core Generator, Viewlogic, synthesis,
viewsynthesis, vhdl

Urgency: Standard

How to incorporate CORE Generator modules in a Viewlogic
Synthesis Flow (Viewsynthesis).


1) Create a Viewlogic Project Directory.

e.g., c:\proj\myproj

2) Create a Project from the WVOffice Project manager
selecting the following libraries:

dir [p] c:\ proj\myproj
dir [w] c:\ proj\myproj (coregen)
dir [rm] c:\wvoffice\unified\xc4000e (xc4000e)
dir [w] c:\wvoffice\unified\logiblox (logiblox)
dir [rm] c:\wvoffice\unified\builtin (builtin)
dir [rm] c:\wvoffice\unified\xbuiltin (xbuiltin)

3) Start Coregen from the Windows Start menu by selecting
"Coregen" from the Xilinx Core Generator shortcut folder.

4) Set the output format options by clicking on
Options->Output Format and select:


- Viewlogic Schematic Symbol
- VHDL Instantiation Template
- VHDL Behavioral Simulation Netlist
- XNF Implementation Netlist

Note that the Viewlogic Schematic Symbol option is required,
for integration into Viewsynthesis even though you may only be
using VHDL in your design flow.

5) Check that all your paths are set properly by looking at
the menu Options->System Options. Only the ProjectPath
setting should require modification by the user. Modify
this path to point to


6) Select the module that you want to generate by clicking on
the file icon corresponding to that Core application.

7) For each module, a Data Sheet is available. Click on the
green and yellow Icon labeled "Spec" to access the Data Sheet.
The module description is included here.

8) Fill out the fields as directed in the CORE Generator
Parameters section of the Data Sheet and click on GENERATE.

Note: Do not name the Module with a Unified Library Name or
Viewsynthesis will use the XNF for the corresponding Unified
Library component instead of the one generated by CoreGen.

9) A Viewlogic symbol, a WIR file, a VHI file (VHDL
instantiation template), and an XNF Netlist File are created.

- A symbol of type Composite is created and placed in the
Viewlogic project SYM directory.
- The WIR file is created from the XNF file and placed in the
Viewlogic project WIR subdirectory.
- The XNF file is placed directly in the Viewlogic project

The VHDL instantiation template contains the component
declaration as well as the Port Map declaration for the
COREGen module and can be Copied and Pasted into the Top Level
VHDL file as shown in the following example:

****** 8 Bit Adder VHDL Instantiation Template: ad8.vhi *******

component ad8 port (
a: IN std_logic_VECTOR(7 downto 0);
b: IN std_logic_VECTOR(7 downto 0);
s: OUT std_logic_VECTOR(8 downto 0);
c: IN std_logic;
ce: IN std_logic;
ci: IN std_logic;
clr: IN std_logic);
end component;

yourInstance : ad8 port map (
a => a,
b => b,
s => s,
c => c,
ce => ce,
ci => ci,
clr => clr);


********** Top Level VHDL file: add8_top.vhd ******

Library IEEE;
use IEEE.std_logic_1164.all;

entity add8_top is
port ( INA,INB: in STD_LOGIC_VECTOR (7 downto 0);
CLK, ce, ci, clr: in STD_LOGIC;
QOUT: out STD_LOGIC_VECTOR (8 downto 0));
end add8_top;

architecture BEHAV of add8_top is

-- Instantiate the ad8.xnf file.

component ad8 port (
a: IN std_logic_VECTOR(7 downto 0);
b: IN std_logic_VECTOR(7 downto 0);
s: OUT std_logic_VECTOR(8 downto 0);
c: IN std_logic;
ce: IN std_logic;
ci: IN std_logic;
clr: IN std_logic);
end component;


u1 : ad8 port map (
a => ina,
b => inb,
s => qout,
c => clk,
ce => ce,
ci => ci,
clr => clr);

end BEHAV;


1- Load the toplevel.vhd file in Viewsynthesis (i.e.,

2- Under the Global Synthesis settings, Select "Generate

3- Compile and synthesize the code,

4- From WVOffice Schematic Entry, load the ad8 symbol and
change the Type to "Module": Open the "Symbol Properties"
window by double clicking on the left mouse button and
changing the symbol type to MODULE. Save the Symbol.

5- Open the top level schematic and add the following
attribute to the ad8 symbol: FILE=ad8.xnf.

6- Since Viewsynthesis does not always recognize the clock
signal, replace the IBUF symbol driving the CLK net with
the Primary Global Buffer BUFGP. Save the Schematic.

7- Open the Xilinx Design Manager and select the top level
WIR file (ie:add8_top.1). Select "Translate", then

AR# 2546
日期 03/27/2000
状态 Archive
Type 综合文章