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Xilinx provides a utility that compiles the HDL libraries for the NC-Verilog simulator. This utility is available at "$XILINX/bin<platform>/compile_hdl.pl" (where <platform> is "hp", "sol", or "nt").
To run this, type the following at the command line:
MANUALLY COMPILING THE MODELS:
Create a library definitions file named "cds.lib". The "cds.lib" file defines which libraries are accessible and where they are located. It also contains statements that map logical library names to their physical directory paths.
Cadence provides a utility called "nclaunch" to set up the necessary initialization files, and to compile the Verilog source libraries. "Nclaunch" is available as part of the 2.1 and later releases. Otherwise, this is a manual process.
The "cds.lib" file can be created with any text editor. The physical locations-to-logical names must also be created before proceeding to the next step. (Use the UNIX command "mkdir".)
mkdir -p <compile_dir>/simprims_ver
If you want the logical library names to be available for all designs, use INCLUDE or SOFTINCLUDE to the location of your master "cds.lib" file.
Edit $CDS_INST_DIR/share/local/xilinx/cds.lib to include:
Create a configuration variables file called "hdl.var". The "hdl.var" file defines variables that determine how the user environment is configured. The variables (LIB_MAP, VIEW_MAP, WORK) are used to specify the search order of the libraries and views when the elaborator resolves instances.
If you want the variable settings to be available for all designs, use INCLUDE or SOFTINCLUDE to the location of your master "hdl.var" file.