General Description: The definition of the "optimization" operation in the context of MAP is the process of doing Xilinx-FPGA specific two-level and multi-level optimization, and device-specific logic packing. The objective is to either decrease the area required by the combinational logic, to reduce the number of logic levels, or both.
This solution discusses when the -os and -oe optimization options in Map should be used.
-os option (default is NO optimization):
The MAP '-os' option allows you to enable OPTX optimization in the Mapper, and also allows you to select an optimization style targeting maximum speed, area, or a balance of speed and area.
-oe option (default is normal):
The -oe option specifies the optimization effort level of the Map OPTX optimizer. When Map is run with the -oe option set to HIGH, the Map logic optimizer tries to do whatever logic collapsing is possible in the design. It then extracts common logic (common sub-expressions) in order to simplify the logic, followed by logic packing to decrease area or levels of logic.
If the design is already optimized (as in the case of a Synopsys design, or schematics entered using Xilinx Unified Library components), running Map with optimization turned on may give you results that are worse than the original design. Running optimize in Map with a HIGH optimization effort level (-oe high) on an already- optimized design is analogous to trying to reprocess a Synopsys design again through the Synopsys tools--that is, you are optimizing an already-optimized design.
On the other hand, when you specify an optimization effort level of "NORMAL", the logic optimizer does NOT try to do logic collapsing all over again. Instead, it tries to decrease area or levels of logic using area or level-reducing algorithms.
Specifying an optimization effort level of "NORMAL" is analogous to processing the design with a tool which runs area- or level- reducing logic mapping algorithms. For some designs, processing with "NORMAL" optimization effort mode may improve performance if the algorithms are able to reduce the area or logic levels in the design.
The general recommendation is not to specify the HIGH optimization effort level (-oe high) on a design that has already been optimized. "-oe HIGH" must be specified only if the design is the output of a VHDL compiler that does not run logic optimization algorithms (Metamor and Xabel, for example).