UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2700

1.5i MAP ERROR:basnu - logical block "core/data" of type "INC_DEC_TWO_COMP_6" is unexpanded.

Description

Keywords: NGDBUILD, MAP, unexpanded, synopsys, edif

Urgency: HOT

Problem Description:
A design compiled with Design Compiler may get a warning
about an unexpanded block from ngdbuild, followed by
an error from map on the same unexpanded block. This
unexpanded block may be DesignWare component that
does exist in the xdw_xcXXXX.sldb file, like an
INC_DEC_TWO_COMP_6, ADD_SUB_UB_12, etc.

解决方案

1

Resolution 1:
Add following synthesis attributes into .synopsys_dc.setup file.
Or use Xilinx template for .synopsyy_dc.setup at
$XILINX/synopsys/examples/template.synopsys_dc.setup_dc.
Refer to Synopsys IVIEW on-line docuementation for more
information on the following attributes.



edifout_netlist_only = true
edifout_no_array = true


2

Your .synopsys_dc.setup file may be missing some of the
required EDIF writer settings. Use the template.synopsys_dc.setup_dc
file as a reference for your .synopsys_dc.setup file.

The template.synopsys_dc.setup_dc can be found in
$XILINX/synopsys/examples
AR# 2700
创建日期 08/20/1997
Last Updated 03/27/2000
状态 Archive
Type 综合文章