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AR# 2713

SYNPLIFY - How do I instantiate an optimized netlist (XNF, EDIF, NGC, COREGEN, LOGIBLOX) file as a black box in HDL (Verilog/VHDL)?

Description


General Description:

How do I instantiate an optimized netlist (XNF, EDIF, NGC, COREGen, LogiBLOX) file as a black box in the Synplify HDL flow?

解决方案


Use the syn_black_box attribute to specify that an instantiated component is a black box (e.g., that

only its interface is defined for synthesis).



When to use black boxes:



- Xilinx primitive instantiation



- User-designed macros whose functionality is defined in a schematic editor other input source.



NOTE: The bus-notation used in the Synplify netlist and the pre-optimized netlist must match.

Please see (Xilinx Solution 4272) for more information. The EDIF format generated in Synplify 5.x

differs in bus notation from the XNF output file previously generated in versions 3.0 and below.



+------+------+------+------------------------------+

| Ver. | 3.x | 5.x | Comments |

+------+------+------+------------------------------+

| XNF | B<|> | B<|> | Bus signals expanded |

+------+------+------+------------------------------+

| EDIF | X | B(I) | Not using "syn_noarrayports" |

+------+------+------+------------------------------+

| EDIF | X | B[I] | Using "syn_noarrayports" |

+------+------+------+------------------------------+



---------------------------------------------

VHDL black box example

---------------------------------------------



library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;



entity tenths_ex is

port ( clkint, clkenable : in STD_LOGIC;

xcountout : out STD_LOGIC_VECTOR(9 downto 0));

end tenths_ex;



architecture xilinx of tenths_ex is



attribute syn_black_box : boolean;



component tenths

port ( CLOCK : in STD_LOGIC;

CLK_EN : in STD_LOGIC;

Q_OUT : out STD_LOGIC_VECTOR(9 downto 0));

end component;

attribute syn_black_box of tenths : component is true;



begin



XCOUNTER : tenths port map( CLOCK => clkint,

CLK_EN => clkenable,

Q_OUT => xcountout

);



end xilinx;



-----------------------------------------------

Verilog black box example

-----------------------------------------------



module tenths_ex (clkint, clkenable, xcountout);

input clkint, clkenable;

output [9:0] xcountout;



tenths XCOUNTER (.CLOCK (clkint), .CLK_EN (clkenable),

.Q_OUT (xcountout));



endmodule



module tenths (CLOCK, CLK_EN, Q_OUT) /* synthesis syn_black_box */;

input CLOCK, CLK_EN;

output [9:0] Q_OUT;



endmodule
AR# 2713
创建日期 08/31/2007
Last Updated 02/20/2012
状态 Archive
Type 综合文章